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Source note3 min read

ArchAgent v2: A Case Study with the Data Prefetching Championship

Source

arXiv

arxiv.org/abs/2608.09874v1

Read the source

Source

  • Source name: arXiv
  • Source kind: paper
  • Authors / organization: Abraham Gonzalez, Raghav Gupta, Akanksha Jain, Hanna Alam, Alexander Novikov, Po-Sen Huang, Matej Balog, Marvin Eisenberger, Sergey Shirobokov, Ngân Vũ, Hank Levy, Borivoje Nikolić, Sagar Karandikar, Martin Dixon, Parthasarathy Ranganathan
  • Venue: arXiv: cs.AI
  • Published: 2026-08-10
  • Collected: 2026-08-11
  • URL: http://arxiv.org/abs/2608.09874v1
  • PDF: https://arxiv.org/pdf/2608.09874v1
  • DOI: UNKNOWN
  • Registry group: academic_apis_and_preprints
  • Evidence role: canonical_academic_index
  • Language: en
  • Country / region: UNKNOWN

Plain-Language Brief

The paper presents ArchAgent v2, a framework that automates the discovery of multi-level data prefetching in computer microarchitecture. It outperforms hand-designed solutions from the 4th Data Prefetching Championship and offers insights into how automated evolutionary agents can explore and synthesize complex microarchitectural logic.

What the Document Says

  • The paper discusses ArchAgent v2, a framework for automating microarchitecture search in computer systems.
  • ArchAgent v2 focuses on multi-level data prefetching, addressing the challenges of vast search spaces, strict hardware budgets, and long simulation times.
  • Two new additions to ArchAgent are introduced: cascaded evolutionary search and a hardware-realizability feedback loop.
  • The cascaded evolutionary search subdivides the design space by evolving and freezing prefetchers at individual cache levels.
  • The hardware-realizability feedback loop embeds real-time size-estimation into the evolution process.
  • Evaluation under DPC4 rules shows that ArchAgent v2 outperforms the winning hand-designed solution and prior champion BertiGO in terms of IPC speedup.
  • The discovered policy achieves a 3.8% geometric mean IPC speedup over the baseline overall and a 0.3% improvement over BertiGO.
  • On low-bandwidth single-core configurations, the policy yields a 4.6% performance speedup compared to 2.6% for BertiGO.
  • However, multi-core evolution remains a challenge due to simulation latency impeding evolution speed.
  • Profiling of over 12,000 candidate designs provides insights into how automated evolutionary agents explore and synthesize complex microarchitectural logic.

Key Concepts Mentioned

  • ArchAgent v2
  • microarchitecture search
  • data prefetching
  • evolutionary search
  • hardware-realizability feedback loop
  • 4th Data Prefetching Championship (DPC4)
  • IPC speedup

Claims Made by the Document

  • ArchAgent v2 outperforms hand-designed solutions from DPC4.
  • The discovered policy achieves a significant IPC speedup over the baseline and prior champion.
  • Multi-core evolution remains a challenge.

Evidence Used

  • Evaluation under identical rules of DPC4
  • Performance speedup numbers provided

Methods / Approach

  • Cascaded evolutionary search
  • Hardware-realizability feedback loop

Limitations Stated by the Authors

  • Multi-core evolution remains a challenge due to simulation latency.

Limitations Noted by the Agent

Agent interpretation — not from the source.

  • The paper does not discuss the implementation details of ArchAgent v2.
  • The paper does not provide detailed comparison with other automated microarchitecture search techniques.

Open Questions

  • What are the specific challenges and solutions for multi-core evolution?
  • How does ArchAgent v2 compare to other automated microarchitecture search techniques?

Notes for Future Q&A

May include interpretation. Labeled where it does.

  • Ask about the implementation details of ArchAgent v2.
  • Ask about comparisons with other automated microarchitecture search techniques.

Raw Abstract / Excerpt

Agentic artificial intelligence has shown great promise in automating algorithm design, but scaling similar techniques to computer microarchitecture discovery remains challenging due to vast search spaces, strict hardware budgets, and long simulation times. In this work, we present ArchAgent v2, a framework which scales automated microarchitecture search to multi-level data prefetching. While the original ArchAgent successfully discovered single-level cache replacement policies in competition settings, it does not scale to multi-level prefetching where the design space and degrees of freedom are larger. To overcome this, we introduce two new additions to ArchAgent: a cascaded evolutionary search that subdivides the design space by sequentially evolving and freezing prefetchers at individual cache levels, and a hardware-realizability feedback loop that embeds real-time size-estimation directly into the evolution process. Evaluated under identical rules of the 4th Data Prefetching Championship (DPC4), ArchAgent v2 automatically designs a three-level prefetcher that outperforms the winning hand-designed solution, further demonstrating automated agentic discovery as a useful tool for computer architects. Our discovered policy achieves a 3.8% geometric mean IPC speedup over the baseline overall and a 0.3% improvement over the prior champion, BertiGO. On low-bandwidth single-core configurations, our policy yields a 4.6% performance speedup compared to only 2.6% for BertiGO. However, multi-core evolution still remains a significant challenge due to simulation latency impeding evolution speed. Finally, our profiling of an ArchAgent evolution of over 12,000 candidate designs provides key insights into how automated evolutionary agents explore and synthesize complex microarchitectural logic.